1. Field of the Invention
The present invention relates generally to the formation of solder joints to electrodes on a substrate, and more particularly, to coaxial solder bump support structures and method of manufacturing the same.
2. Description of the Related Art
Solder bumps are commonly used as an electrical connection between semiconductor chips and ceramic or organic substrates used to connect to the outside world. There are a variety of techniques that may be employed to connect the solder bump to the chip. One such technique utilizes one or more layers of protective material coated onto the finished chip to protect the last level of metallization from mechanical handling damage and corrosion or oxidation. This technique typically involves forming a via in the protective material in order to connect the solder to the last metallization layer. Once the solder bumps are deposited onto the chip, the chip is then joined to the substrate by positioning the chip so that the solder bumps are aligned with the appropriate pads on the substrate, then heated in a furnace to above the melting point of the solder. Because the substrate has a much larger coefficient of thermal expansion (CTE) than the chip, the substrate typically shrinks more than the chip during cooling to room temperature, causing shear stresses to develop on the solidified solder bumps. As the difference in the relative displacement between the surface of the substrate and that of the chip varies in proportion to the distance from the center of the chip, the outermost solder bumps experience the largest shear stresses.
The shear stresses resulting from the CTE mismatch exert a rotating moment on the solder bumps that is perpendicular to the radial direction from the center of the chip and the solder bump. This rotational energy typically causes tensile stress to be concentrated at the outer edge of the solder bump where it comes into contact with the chip, and this tensile stress acts to pull the solder away from the surface of the chip. If the last insulating layer on the chip is more compliant than the hard dielectrics that form the wiring insulation (for example, if the last insulation layer is a polyimide), the insulating layer can flex slightly in such a way that under repeated thermal cycles, or even during the cool down process from chip joining, the tensile stress can be transferred from the interface between the last conductive layer and the softer dielectric inward to the edge of the via. When either the above described heat treatment steps are repeated a large number of cycles or the tensile stress is of great enough magnitude, thermally induced solder bump cracks will result.
The mechanical properties of the protective insulator material that is found between the last metallization level and the solder bump play a large role in the amount of stress transferred to the chip. If the protective insulator level is more elastic, the solder bump and its correlating bump pad is able to flex more with the higher CTE substrate. Different types of protective insulator materials have their own advantages and disadvantages. For example, some protective insulator materials may have a very beneficial elasticity but also have a very high residual stress, which causes excessive wafer warp and bow. The term “warp”, as used herein, refers to the maximum deviation between any location on a wafer and a plane passing through the center of gravity of the wafer mounted free of forces. The term “bow”, as used herein, refers to the maximum deviation between any location on a wafer mounted free of forces and a plane which is defined by three points on the wafer forming an isosceles triangle. The bow is generally included in the warp and cannot be greater than the warp.
Typically, thickening the protective insulator material also proves to be beneficial for mitigating the stresses caused by the CTE mismatch of the chip and the substrate, but, unfortunately, this technique also increases the warp of the wafer as a whole. One should keep the bow and warp of the wafer within specifications to ensure that the subsequent semiconductor processing operations can be performed. Accordingly, it is desirable to provide solder bump support structures and method for fabricating those solder bump support structures with reduced wafer bow and warp.